In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities, there has been and continues to be efforts toward scaling down device dimensions (e.g., at submicron levels) on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are required in integrated circuits (ICs) fabricated on small rectangular portions of the wafer, commonly known as dies. This can include width and spacing of interconnecting lines, spacing and diameter of contact holes, surface geometry such as corners and edges of various features as well as surface geometry of other features. To scale down device dimensions, more precise control of fabrication processes are required. The dimensions of and between features can be referred to as critical dimensions (CDs). Reducing CDs, and reproducing more accurate CDs facilitates achieving higher device densities through scaled down device dimensions and increased packing densities.
The process of manufacturing semiconductors or ICs typically includes numerous steps (e.g., exposing, baking, developing), during which hundreds of copies of an integrated circuit may be formed on a single wafer, and more particularly on each die of a wafer. In many of these steps, material is overlayed or removed from existing layers at specific locations to form desired elements of the integrated circuit. Generally, the manufacturing process involves creating several patterned layers on and into a substrate that ultimately forms the complete integrated circuit. This layering process creates electrically active regions in and on the semiconductor wafer surface.
Lithography is one particular process utilized in semiconductor processing and/or manufacturing. Lithography generally refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the photoresist. Thereafter, an exposing source (such as optical light, X-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template (e.g., a photoresist mask) for a particular pattern. The lithographic coating is generally a radiation-sensitized coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive of the subject pattern. Exposure of the coating through the photoresist mask causes a chemical transformation in the exposed areas of the coating thereby making the image area either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer. The resulting pattern image in the coating, or layer, may be at least one portion of a semiconductor device that contributes to the overall structure and function of the device.
Due to continuous shrinking of design dimensions, precision during patterning is of increasing importance. As these design dimensions are reduced, monitoring, controlling, and correcting line edge roughness (LER) resident upon a semiconductor substrate is becoming essential to maintain adequate device yield. LER refers to a measurement of irregularity on a semiconductor substrate from a perfectly rectilinear profile, wherein such irregularity can occur during patterning. Conventional systems and/or methodologies for measuring and/or correcting LER are proprietary, and they utilize independently developed measurement algorithms. Thus, differing measurement/correction tools will provide dissimilar LER measurements for a single line/structure. Correction measures therefore will be dependent upon the metrology tool, and such non-uniformity between metrology tools can lead to inefficient design and manufacturing of integrated circuits. For example, a structure can be measured by three disparate metrology tools, the tools finding the roughness to be of measurement M1, M2, and M3, respectively. M1 may be within manufacturing specifications, while M2 and M3 may be outside such specifications. Because one fab includes a large number of metrology tools, determining an amount of correction for different tools can require substantial resources and result in lack of efficiency during integrated circuit manufacturing. As such, metrology tools and algorithms cannot be compared and correlated with manufacturing device performance.
Accordingly, there is a need in the art for a tool independent system and/or methodology for measuring and correcting line edge roughness.